1. Field of the Invention
The present invention relates generally to a non-real-time Operating System (OS), and in particular, to an apparatus and method of time keeping for accurate time scheduling in a non-real-time OS.
2. Description of the Related Art
The existing systems require a real-time OS guaranteeing a short response time. When several processors contend for the same resource, the real-time OS can prevent a collision (locking) due to the contention based on the short response time. However, in the case of an OS providing hard real-time characteristics, an increase in the system complexity causes an increase in the design cost for the OS.
A method of designing a stable system without using the real-time OS is to design a system in such a way that there is no load in the processing capacity with a sufficient margin in hardware resources. However, the sufficient hardware resource margin also causes an increase in the design cost. Therefore, the best method is to use a non-real-time OS in the system design stage and implement a hardware system in such a way that the OS and the hardware are complementary to each other.
A channel card of the existing system includes a Network Processor Unit (NPU), a Digital Signal Processor (DSP), and a Dual-Port Random Access Memory (DPRAM) supporting data communication between the NPU and the DSP. The NPU processes non-real-time packet data using a non-real-time OS. The NPU supports a Peripheral Component Interconnect (PCI) bus interface and communicates with an external processor connected through a PCI bus. On the other hand, the DPRAM does not support a PCI bus interface and thus uses a PCI Field Programmable Gate Array (FPGA) for matching between the DPRAM itself and the PCI bus of the NPU.
The DPRAM uses a Time Division Multiple Access (TDMA) scheme to prevent a collision due to the simultaneous access of the two processors. A predetermined area of the DPRAM serves as a flag area and the two processors access the flag area in a TDMA scheme, so that a write/read (W/R) operation is performed according to a flag value of the flag area. Therefore, if the two processors support a short response time, a collision due to the simultaneous DPRAM access of the two processors can be prevented. When a hard real-time OS is used for both the NPU and the DSP for an accurate TDMA scheme, the above method has no problem. However, when a non-real-time OS is used as in the currently existing system, the DPRAM access time of the NPU is not constant with a time interval defined in a DPRAM access time table but varies depending on the load of the processor (i.e., NPU), which causes data corruption in communication between the two processors (i.e., the NPU and the DSP).
The NPU based on the non-real-time OS is constructed to include two cores, i.e., a X-scale and a Micro Engine (ME). An Interrupt Service Routine (ISR) of the X-scale transmits a system clock (i.e., real time information) to the ME. The ME executes tasks using an internal timer that operates according to the real time information. However, if there is a large amount of internal load for a predetermined time period, the ME may fail to read the real time information from the X-scale while processing the internal load. In this case, errors may occur in the system clock and the internal timer of the ME. Thus, the ME, which writes data on the DPRAM through a PCI bus according to the internal timer, may fail to try the DPRAM access within the predetermined time interval of the access time table.